Physically aware scan diagnostic logic and power saving circuit insertion

ABSTRACT

Aspects include a computer-implemented method for scan diagnostic logic circuit insertion in a circuit design topology. A method includes evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain. The method also includes identifying one of the plurality of physical structures as a physical structure of interest, and responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain.

BACKGROUND

The present disclosure relates generally to circuit design testing, andmore specifically, to a physically aware scan diagnostic and powersaving circuit insertion.

A scan chain is a technique used in design for testing the topology ofan integrated circuit (IC) in order to make testing easier by providinga simple way to set and observe every flip-flop/latch in the IC. Scandiagnostic logic insertion is generally required in order to diagnosefailing scan chains, and scan fails are a significantly large percentageof IC fails throughout the life of the product. Difficulties inisolating specific structures arise because of the overhead required toperform the failure analysis. Resolution down to the exact failing latchposition could be made possible through diagnostic logic insertion atevery single latch position, but this would be inefficient andimpractical. Realistically, scan diagnostic logic can only be placed ona small fraction of the existing scan nets on an IC, and for successfulfailure analysis, generally only a small limited area of localization isrequired as there are trade-offs between the diagnostic resolution sizeand the scan diagnostic logic overhead.

Long scan nets in the scan chain create other additional concerns duringscan chain analysis. They are a significant contributor to theconsumption of functional chip power when allowed to switch during thefunctional operation of the chip, and power is generally consumed whennot in a scanning mode by these long scan nets adding to the overallinefficiency of the scan chain analysis. Additionally, long scan netsare likely to have defects due to their large critical area and thenumber of shapes they occupy.

SUMMARY

According to embodiments, a method, system, and computer program productfor implementing scan diagnostic logic insertion in a circuit designtopology. A method includes evaluating a scan chain of the circuitdesign topology, the scan chain comprising a plurality of scan latchesand a plurality of physical structures, the evaluating includingidentifying the plurality of physical structures in the scan chain. Themethod also includes identifying one of the plurality of physicalstructures as a physical structure of interest, and responsive to theidentification of the physical structure of interest, targeting thephysical structure of interest, the targeting comprising inserting scandiagnostic logic at a location in the scan chain that is based on alocation of the physical structure of interest in the scan chain.

Additional features and advantages are realized through the techniquesof the invention. Other embodiments and aspects of the invention aredescribed in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating one example of a processingsystem for practice of the teachings herein;

FIGS. 2A and 2B are flow diagrams for performing physically aware scandiagnostic and power saving circuit insertion in accordance with one ormore embodiments;

FIG. 3 is a block diagram illustrating a scan chain in accordance withone or more embodiments;

FIG. 4 is a block diagram illustrating an exemplary embodiment forphysically aware scan diagnostic and power saving circuit insertion;

FIG. 5 is a block diagram illustrating another exemplary embodiment forphysically aware scan diagnostic and power saving circuit insertion;

FIG. 6 is a block diagram illustrating scan diagnostic logic inaccordance with one or more embodiments; and

FIG. 7 is a block diagram illustrating alternative scan diagnostic logicin accordance with one or more embodiments.

DETAILED DESCRIPTION

In accordance with embodiments of the disclosure, physically aware scandiagnostic and power saving circuit insertion is provided. Embodimentsdescribed herein include techniques for using physical awareness in thetargeting of inserting scan diagnostic logic, scan isolation logic, andscan net power saving logic

Referring to FIG. 1, there is shown an embodiment of a processing system100 for implementing the teachings herein. In this embodiment, thesystem 100 has one or more central processing units (processors) 101 a,101 b, 101 c, etc. (collectively or generically referred to asprocessor(s) 101). In one embodiment, each processor 101 may include areduced instruction set computer (RISC) microprocessor. Processors 101are coupled to system memory 114 and various other components via asystem bus 113. Read only memory (ROM) 102 is coupled to the system bus113 and may include a basic input/output system (BIOS), which controlscertain basic functions of system 100.

FIG. 1 further depicts an input/output (I/O) adapter 107 and a networkadapter 106 coupled to the system bus 113. I/O adapter 107 may be asmall computer system interface (SCSI) adapter that communicates with ahard disk 103 and/or tape storage drive 105 or any other similarcomponent. I/O adapter 107, hard disk 103, and tape storage device 105are collectively referred to herein as mass storage 104. Operatingsystem 120 for execution on the processing system 100 may be stored inmass storage 104. A network adapter 106 interconnects bus 113 with anoutside network 116 enabling data processing system 100 to communicatewith other such systems. A screen (e.g., a display monitor) 115 isconnected to system bus 113 by display adaptor 112, which may include agraphics adapter to improve the performance of graphics intensiveapplications and a video controller. In one embodiment, adapters 107,106, and 112 may be connected to one or more I/O busses that areconnected to system bus 113 via an intermediate bus bridge (not shown).Suitable I/O buses for connecting peripheral devices such as hard diskcontrollers, network adapters, and graphics adapters typically includecommon protocols, such as the Peripheral Component Interconnect (PCI).Additional input/output devices are shown as connected to system bus 113via user interface adapter 108 and display adapter 112. A keyboard 109,mouse 110, and speaker 111 all interconnected to bus 113 via userinterface adapter 108, which may include, for example, a Super I/O chipintegrating multiple device adapters into a single integrated circuit.

In exemplary embodiments, the processing system 100 includes a graphicsprocessing unit 130. Graphics processing unit 130 is a specializedelectronic circuit designed to manipulate and alter memory to acceleratethe creation of images in a frame buffer intended for output to adisplay. In general, graphics processing unit 130 is very efficient atmanipulating computer graphics and image processing, and has a highlyparallel structure that makes it more effective than general-purposeCPUs for algorithms where processing of large blocks of data is done inparallel.

Thus, as configured in FIG. 1, the system 100 includes processingcapability in the form of processors 101, storage capability includingsystem memory 114 and mass storage 104, input means such as keyboard 109and mouse 110, and output capability including speaker 111 and display115. In one embodiment, a portion of system memory 114 and mass storage104 collectively store an operating system to coordinate the functionsof the various components shown in FIG. 1. The system 100 can beimplemented in order to perform the testing of various semiconductorsand IC devices.

Referring now to FIGS. 2A and 2B, a flow diagram 200 for performingphysically aware scan diagnostic logic circuit insertion in a circuittopology is generally shown in accordance with an embodiment. At block204 a scan chain of the design topology that includes a plurality ofscan latches and a plurality of physical structures is evaluated, theevaluating includes identifying the plurality of physical structures inthe scan chain. Block 206 shows identifying one of the plurality ofphysical structures of interest as a physical structure of interest inthe scan chain. In an exemplary embodiment the physical structure ofinterest is at least one of a scan path, long scan net, a specific metallevel, and a specific latch type. Scan paths include any connectionbetween two adjacent latches. Additionally scan paths may comprisemultiple scan nets and other logic devices (buffers). In an exemplaryembodiment, the physical structure of interest includes scan paths. Inother embodiments, the physical structure of interest may be a long scannet. The long scan nets may be selected for analysis as long scan netsare likely to have defects due to their large critical area and numberof shapes they occupy. A scan net may be determined to be a long scannet based on a design metric. In an exemplary embodiment, the designmetric is a configurable threshold length used to determine whether ascan net length exceeds the threshold. If it is determined that thethreshold is exceeded, a scan diagnostic logic can be added at thebeginning of each long scan net for power conservation, and another scandiagnostic logic can be added after the next latch in the scan chain toisolate the long scan net. Targeted insertion of a scan diagnostic logicat the beginning of these long scan nets can save the majority of scannet functional power while minimizing the circuitry requirements neededto accomplish such. Physically aware targeted scan diagnostic logicinsertion can benefit chip power reduction. In other embodiments, thedesign metric is associated with device counts. For example, after fourbuffers (logic devices, latches, logic primitives, etc.) the scaninsertion logic is inserted for power conservation. The design metricsas described are intended to be exemplary in nature, and are notintended to strictly limit is scope.

At block 208, responsive to the identification of the physical structureof interest at block 206, the physical structure of interest istargeted, the targeting including inserting scan diagnostic logic at alocation in the scan chain that is based on a location of the physicalstructure of interest in the scan chain. In an exemplary embodiment thetargeting includes inserting scan diagnostic logic into the scan chainwhere the scan diagnostic logic may be of a multiplexor configuration ora NOR/XNOR configuration. A diagnostic analysis of the scan chain isexecuted based on the targeted physical structure of interest and thescan diagnostic logic.

In an exemplary embodiment, targeting the physical structure of interestincludes inserting a scan diagnostic logic at a location that isupstream from the physical structure of interest in the scan chain asshown in block 220 of FIG. 2B. The location upstream from the physicalinterest is a location occurring prior to the physical structure ofinterest in the scan chain. The location of the scan diagnostic logicallows the disabling of the scan chain segment to conserve power whenthe system is operating in a functional mode. When the circuit isoperating in a functional mode, the scan diagnostic logic insertedupstream the physical structure of interest can be controlled to disablethe scan chain segment including the physical structure of interest toconserve energy. Similarly the scan chain segment can be enabled usingthe global signals during a scan diagnostic mode. In another exemplaryembodiment the selected physical structure of interest can be isolatedfor failure analysis. Block 222 provides isolation of the physicalstructure of interest by inserting a scan diagnostic logic upstream fromthe physical structure of interest and the location in the scan chainthat is downstream from the physical structure of interest that isimmediately after a downstream scan latch, where the downstream latch isone of the plurality of scan latches of the scan chain. The locationdownstream the physical structure of interest occurs at a location afterthe physical structure of interest in the scan chain that is oppositethe upstream direction. The downstream scan latch is located adjacent tothe physical structure of interest.

In an exemplary embodiment, further granularity in testing may bedesired, and FIG. 2B at block 224 provides for inserting additional scandiagnostic logic at a segment size resolution subsequent to thetargeting and/or isolation of the physical structure of interest,wherein the segment size resolution is based on a number of scanlatches. In an exemplary embodiment, the segment size is configurable.Block 226 provides for controlling the scan diagnostic logic by applyinga global signal to the inserted scan diagnostic logic. In an exemplaryembodiment, the global signals are signals that can be applied to one ormore scan diagnostic logics in the scan chain either individually or incombination with other scan diagnostic logics. In another embodiment,the global signals include a scan input signal, scan diagnostic signal,scan disable signal, and other global signals known to one of ordinaryskill in the art. In another exemplary embodiment, a scan disable signalis applied to the scan diagnostic logic to disable the scan elements inthe scan chain when a scanning operation is not being executed. Sincelong nets use significant amounts of power and have large capacitance,the targeting of the long scan nets as the physical structure ofinterest may be implemented to conserve power of the circuit. Whenimplementing the power saving feature, the technique only requires ascan insertion logic to be inserted prior to the large power burningscan nets of interest, and no further scan insertion logic is neededafter the next downstream latch.

In another exemplary embodiment, isolation of the physical structure ofinterest may be implemented for a localized failure analysis of a scanchain segment. In a different embodiment a combination of targeting aphysical structure for power conservation and isolation of the physicalstructure of interest can be implemented. In another exemplaryembodiment the scan diagnostic logic may be inserted at a configurablesegment size resolution. Any of the above techniques may be combined forperforming the scan chain diagnostic.

FIG. 3 shows an example of an existing scan chain 300 for performingfailure analysis in accordance with an embodiment. Scan chain 300includes a plurality of latches 302-312, where latch 302 receives aninput signal 322. A scan diagnostic logic 316 is placed after every fourlatches, and receives as an input a scan diagnostic signal 324 foranalyzing the scan chain 300. In this example the segment sizeresolution is based on four scan latches, which determines the placementof each of the scan diagnostic logic. Scan chain 300 further includeslong scan nets 318 and 320 which consume power from the system.

Referring now to FIG. 4, a scan chain 400 in accordance with anexemplary embodiment is shown. Scan chain 400 includes a plurality oflatches, long scan nets, and scan diagnostic logic. Latches 402-418 areincluded in the scan chain where latch 402 receives an input signal 430to the scan chain. In this exemplary embodiment, the scan diagnosticinsertion logic 420 and 422 is a mux device which receives globalsignals such as a scan diagnostic signal 432 and a scan disable signal434. In an exemplary embodiment the scan diagnostic logic is implementedwith targeted power saving of scan chain 400. The location of the scandiagnostic logic 420 and 422 are positioned in a location to reducepower consumption. When implementing the power saving feature, a scaninsertion logic is only required to be inserted prior to the physicalstructure of interest (large power burning scan nets) and no furtherscan diagnostic logic is needed after the next latch. In an exemplaryembodiment, the physical structures of interests can be long scan nets424 and 426. When power saving is implemented a scan_disable signal 434is provided to each scan diagnostic logic (420 and 422) of the scanchain to prevent the switching of the long scan nets 424 and 426 whenthere is no scan chain failure analysis being performed. An outputsignal is provided at 436.

Now referring to FIG. 5, a scan chain 500 according to an exemplaryembodiment is generally shown. The scan chain 500 includes a pluralityof latches 502-518 and a plurality of scan diagnostic logics 520-526. Inthis exemplary embodiment, the scan diagnostic logic 520-526 is amultiplexor (mux) device. It is known to one of ordinary skill in theart that other types of scan diagnostic logic, gates, or circuits can beused. Latch 502 is configured to receive an input signal 530 and scandiagnostic logic 520-526 is configured to receive global signalsincluding a scan_diagnostic signal 532 and a scan_disable signal 534. Anoutput of the scan chain is provided at output 536. Scan chain 500further includes long scan nets 540 and 542. In an exemplary embodiment,the scan diagnostic logic insertion is implemented for targeted powersaving and diagnostic isolation of physical structures of interest. Thelong scan nets 540 and 542 consume substantial amounts of power and scandiagnostic logic 520 and 524 are inserted at the beginning of each ofthe long scan nets 540 and 542. In addition, the long scan nets 540 and542 are isolated by inserting another scan diagnostic logic 522 and 526after a next downstream latch 508 and 514, respectively. In an exemplaryembodiment, the long nets 540 and 542 are analyzed for defects orfailures and the scan diagnostic logic 520 and 524 are able to receive ascan_disable signal 534 to conserve power in the system when scanning isnot being performed. In this manner power conservation and efficientisolation can be achieved.

Now referring to FIG. 6 an exemplary scan diagnostic logic 600 is shown.A scan_in signal 608 is provided to an input signal latch 602, and ascan_diagnostic signal 610 is provided to a scan insertion logic mux604. A scan_disable signal 612 is provided to disable mux 604 toconserve power when a scan diagnostic is not being executed and preventsthe switching of a connected circuit element. An output 614 is providedby scan latch 606.

FIG. 7 depicts an exemplary scan diagnostic logic NOR/XNORconfiguration. Scan_in signal 710 is provided to latch 702 where latch702 is coupled to NOR gate 704. The NOR gate 704 is further coupled toXNOR gate 706. NOR gate 704 is configured to receive a scan_disablesignal 712 and XNOR gate 706 is configured to receive a scan_diagnosticsignal 714. An output is provided at output 716. XNOR gate 706 iscoupled to latch 708. These global signals can be invoked to control thescan diagnostic logic to implement power conservation and scan chainanalysis.

Technical effects and benefits include targeted scan diagnostic logicinsertion that is highly efficient in that it requires very fewadditional scan diagnostic logic/gates, when compared to existingmethods (e.g., of only placing gating elements at an arbitrary N numberof latches). Benefits can include performing a scan diagnosticoperation, where a break in the scan chain located at a particularphysical structure of interest can be identified down to the resolutionof one latch position. High resolution at low overhead cost can beachieved for the scan chain analysis thereby improving processing timeand power. Additionally, in the case of a long wire, the functionalpower burn caused by that long scan wire can be eliminated by using thescan diagnostic logic to block the switching of that wire duringfunction operation.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

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 9. A computer program product for performing scan diagnostic logic insertion in a circuit design topology, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor located on a device to cause the computer processor to perform: evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain; identifying one of the plurality of physical structures as a physical structure of interest; and responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain.
 10. The computer readable medium of claim 9, wherein the physical structure of interest is at least one of a scan path, a long scan net, a metal layer, and a specific latch type.
 11. The computer readable medium of claim 9, the scan diagnostic logic is inserted at a location that is upstream from the physical structure of interest.
 12. The computer readable medium of claim 9, further comprising isolating the physical structure of interest, the isolating comprising inserting additional scan diagnostic logic at a location in the scan chain that is downstream from the physical structure of interest.
 13. The computer readable medium of claim 12, wherein the scan diagnostic logic at a location in the scan chain that is upstream from the physical structure of interest and the location in the scan chain that is downstream from the physical structure of interest is immediately after a downstream scan latch, wherein the downstream scan latch is one of the plurality of scan latches.
 14. The computer readable medium of claim 9, further comprising: controlling the scan diagnostic logic by applying a global signal to the scan insertion logic to prevent switching of the physical structure of interest during functional operation.
 15. The computer readable medium of claim 9, wherein the physical structure of interest is identified based on a design metric.
 16. The computer readable medium of claim 9, further comprising, inserting further scan diagnostic logic at a desired segment size resolution subsequent to the targeting of the physical structure of interest, wherein the segment size resolution is based on a number of scan latches.
 17. A system for scan diagnostic logic insertion in a circuit design topology, the system comprising: a memory having computer readable instructions; a processor for executing the computer readable instructions, the computer readable instructions comprising: evaluate a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain; identify one of the plurality of physical structures as a physical structure of interest, the physical structure of interest comprising at least one of a scan path, a long scan net, a metal layer, or a specific latch type; and responsive to the identification of the physical structure of interest, target the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain.
 18. The system of claim 17, the scan diagnostic logic is inserted at a location in the scan chain that is upstream from the physical structure of interest.
 19. The system of claim 17, wherein the scan diagnostic logic is inserted at a location in the scan chain that is upstream from the physical structure of interest and the location in the scan chain that is downstream from the physical structure of interest is immediately after a downstream scan latch, wherein the downstream scan latch is one of the plurality of scan latches.
 20. The computer readable medium of claim 17, further comprising, inserting further scan diagnostic logic at a segment size resolution subsequent to the targeting of the physical structure of interest, wherein the segment size resolution is based on a number of scan latches. 